Ufs 3.1 Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 A VCC VCC NC REF RST NC NC NC NC NC NC NC NC _CLK _N B VCC VCC C/D VSS VSS NC NC NC NC NC NC NC NC C VCC VCC D0_ D0_ VSS NC NC NC NC NC NC NC NC Q Q RX TX D VCC VCC D1_ D1_ VSS NC NC NC NC NC NC NC NC Q Q RX TX

architecture allows the device to read and write data simultaneously, a major advantage over the half-duplex eMMC standard. Reference Clock (REF_CLK): ufs 3.1 pinout

Typically multiple pins (e.g., A3, B3, C3) for current capacity. I/O Voltage Low voltage rail (1.2V typical). PHY Voltage Mid-range voltage rail (1.8V typical). Transmit Pairs 1 2 3 4 5 6 7 8